The Real AI Infrastructure Supply Chain

Most coverage of the AI boom talks about "chip supply" as if it were one thing. It isn't. It's a chain of dependencies running through a small number of companies, each one a genuine bottleneck in its own right — and understanding where those bottlenecks actually sit matters more than knowing that "chips are tight." This is the version of that chain built from InsightNodes' own graph: real entities, real sourced relationships, not a generic explainer.

It starts with lithography, and there is one company

Every advanced logic chip — NVIDIA's GPUs, AMD's accelerators, Apple's and Google's custom silicon — depends on extreme ultraviolet (EUV) lithography to print features small enough to matter at the leading edge. ASML, based in the Netherlands, is the only company in the world that makes EUV lithography machines. Not the leading company — the only one. TSMC, Samsung, and Intel all depend on ASML directly; there is no second source. That single-supplier dependency is the deepest structural bottleneck in the entire AI hardware stack, and it sits upstream of everything else in this piece.

The foundry layer: design doesn't equal manufacturing

NVIDIA, AMD, and most of the hyperscalers' custom silicon teams (Amazon's Trainium/Inferentia, Google's TPUs, Microsoft's Maia) design chips — they don't manufacture them. That work is concentrated overwhelmingly at TSMC, which holds the leading position in advanced-node (sub-5nm) manufacturing capacity. Samsung Foundry and Intel Foundry both compete for this business, but TSMC's lead at the most advanced nodes has made it the default manufacturing partner for nearly every major AI chip designer — which means a disruption at TSMC (geopolitical, natural disaster, or otherwise) is a single point of failure for the entire industry's chip supply, not just one company's.

Advanced packaging is the newer, less-understood bottleneck

A finished AI chip isn't just a manufactured die — it has to be packaged, and for high-end AI accelerators that means advanced packaging techniques like TSMC's CoWoS (Chip-on-Wafer-on-Substrate), which binds the compute die to high-bandwidth memory stacks. CoWoS capacity has repeatedly been a tighter constraint than raw wafer manufacturing capacity itself — NVIDIA has publicly discussed CoWoS availability as a gating factor on how many GPUs it can actually ship, independent of how many dies TSMC can print. Packaging capacity, not just fab capacity, is now a first-order supply chain variable.

Memory: a three-company market for the part everyone forgets

High-bandwidth memory (HBM) — the memory stacked directly next to the compute die in an AI accelerator — is effectively a three-company market: SK Hynix, Samsung, and Micron. SK Hynix has held the leading position in HBM supply to NVIDIA specifically. Memory is easy to overlook because it isn't the "chip" headline number, but an AI accelerator without sufficient HBM bandwidth is a bottlenecked accelerator regardless of how fast its logic die is — HBM supply agreements are negotiated and secured years in advance for exactly this reason.

Capital and policy sit on top of the physical chain

None of the above happens without capital and policy layered on top. Hyperscalers (Microsoft, Amazon, Google, Meta) commit tens of billions of dollars annually in capital expenditure specifically to secure AI infrastructure buildout, and sovereign capital — Gulf state funds, Singapore's GIC and Temasek, Norway's sovereign wealth fund — increasingly co-invests directly in AI infrastructure and the companies building it. On the policy side, U.S. export controls on advanced AI chips to China have reshaped where leading-edge chips can legally ship, which is a direct reason companies like SMIC (China's leading domestic foundry) and Huawei have pushed hard on domestic alternatives — DeepSeek's own reported pivot of later models toward Huawei's Ascend chips is a direct downstream effect of that policy layer, not a separate story.

Why this matters more as one connected chain than as five separate facts

Each of these five layers — lithography, foundry, packaging, memory, and capital/policy — gets covered separately in most technology news, as isolated headlines: a CoWoS capacity update here, an export control announcement there. But they're one chain. A change at any single layer — an ASML export restriction, a TSMC capacity decision, a CoWoS allocation shift, an HBM supply agreement, a new export control — propagates through every layer below it. That's the actual argument for treating technology as a connected graph instead of a list of headlines, and it's the reason InsightNodes exists: every entity mentioned in this piece — ASML, TSMC, NVIDIA, SK Hynix, and the rest — has its own sourced page in the graph, with the specific relationships described here modeled explicitly rather than left implicit.

Explore the full, sourced version of this chain — including the specific companies, capital, and policy decisions behind it — directly in the graph.